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LTC1983-3/ltc1983-5 1 sn1983 1983fs the ltc ? 1983-3 and ltc1983-5 are inverting charge pump dc/dc converters that produce negative regulated outputs. the parts require only three tiny external capaci- tors and can provide up to 100ma of output current. the devices can operate in open loop mode (creating a Cv in supply) or regulated output mode depending on the input supply voltage and the output current. the LTC1983-3/ltc1983-5 have many useful features for portable applications including very low quiescent current (25 m a typical) and a zero current shutdown mode pro- grammed through the shdn pin. the LTC1983-3/ltc1983-5 are over-temperature and short-circuit protected. the parts are available in a 6-pin low profile (1mm) thinsot package. n C3v generation in single-supply systems n portable equipment n lcd bias supplies n gaas fet bias supplies n fixed output voltages: C3v, C5v or low noise v in to Cv in inverted output n 4% output voltage accuracy n low quiesient current: 25 m a n 100ma output current capability n 3v to 5.5v operating voltage range (LTC1983-3) n 2.3v to 5.5v operating voltage range (ltc1983-5) n internal 900khz oscillator n zero current shutdown n short-circuit and over-temperature protected n low profile (1mm) thinsot tm package 100ma regulated charge-pump inverters in thinsot , ltc and lt are registered trademarks of linear technology corporation. thinsot is a trademark of linear technology corporation. v in shdn c + v out gnd c LTC1983-3 v in 3v to 5.5v v out = ?v i out = up to 100ma c out 10 f c in 10 f c fly 1 f off on c fly : taiyo yuden lmk212bj105 c in , c out : taiyo yuden jmk316bj106ml 1983-3 ta01 v out vs i out i out (ma) 0 v out (v) ?.3 ?.2 ?.1 ?.0 ?.9 ?.8 ?.7 20 40 60 80 1983 ta02 100 v in = 5v v in = 3.3v descriptio u features applicatio s u typical applicatio u C3v at 100ma dc/dc converter
LTC1983-3/ltc1983-5 2 sn1983 1983fs v in to gnd ................................................... C0.3v to 6v shdn voltage .............................................. C0.3v to 6v v out to gnd (LTC1983-3) .................. 0.2v to v out max v out to gnd (ltc1983-5) .................. 0.2v to v out max i out max ............................................................. 125ma output short-circuit duration .......................... indefinite operating temperature range (note 2) ...C40 c to 85 c storage temperature range ................. C 65 c to 125 c lead temperature (soldering, 10 sec).................. 300 c order part number s6 part marking t jmax = 125 c, q ja = 256 c/w consult ltc marketing for parts specified with wider operating temperature ranges. ltpc ltyb ltc1983es6-3 ltc1983es6-5 absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics burst mode is a registered trademark of linear technology corporation. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 5v, c fly = 1 m f, c out = 10 m f unless otherwise noted. parameter conditions min typ max units v in operating voltage (regulated output mode) (LTC1983-3) l 3.0 5.5 v v in min startup voltage 2.3 v v out (LTC1983-3) v in 3 3.3v, i out 25ma l C2.88 C3 C3.12 v v in 3 5v, i out 100ma l C2.88 C3 C3.12 v v out (ltc1983-5) v in 3 5v, v in C5v 3 i out ? r out l C 4.8 C5 C 5.2 v v in operating current v in 5.5v, i out = 0 m a, shdn = v in l 25 60 m a v in operating current (open-loop mode) (ltc1983-5) v in = 3.3v 2.5 ma v in = 4.75v 4 ma v in shutdown current shdn = 0v, v in 5.5v l 0.1 1 m a output ripple 3.3 v in 5.5 60 mv p-p open-loop output impedance (LTC1983-3): r out v in = 3.3v, v out = C3v 11 w open-loop output impedance (ltc1983-5): r out v in = 3.3v, i out ? 50ma 11 w v in = 5v, i out ? 60ma 8.5 w oscillator frequency (non-burst mode ? operation) 900 khz shdn input high l 1.1 v shdn input low l 0.3 v shdn input current v shdn = 5.5v l 2.2 4 m a v cc 1 v out 2 c + 3 6 shdn 5 gnd 4 c top view s6 package 6-lead plastic sot-23 note 2: the ltc1983e-3/ltc1983e-5 are guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls.
LTC1983-3/ltc1983-5 3 sn1983 1983fs output impedance vs input voltage output impedance vs i out (ltc1983-5) efficiency vs i out (ltc1983-5) typical perfor a ce characteristics uw efficiency vs i out i out (ma) 0 efficiency (%) 40 80 100 90 80 70 60 50 40 30 20 10 0 1983 g01 20 60 v in = 2.3v v in = 3.3v v in = 5v t a = 25 c v in (v) 2.35 r out ( ) 4.35 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 1983 ta02 3.35 5.35 r out i out = 25ma t a = 25 c i out (ma) 0 r out ( ) 40 80 100 30 25 20 15 10 5 1983 g03 20 60 v in = 2.3v v in = 3.3v v in = 5v t a = 25 c i out (ma) 0.01 100 75 50 25 0 10 1983 go4 0.1 1 100 efficiency (%) v in = 5v v in = 3.3v v out = ?v t a = 25 c output current (ma) 0 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 60 100 1983 g05 20 40 80 120 v out (v) 120 c ?0 c, 0 c, 40 c 80 c output current (ma) 0 2.7 v out (v) 2.8 2.9 3.0 3.1 3.3 20 40 60 80 1983 g06 100 120 3.2 ?0 c 0 c 40 c 80 c v in = 5v C3v out vs i out over temperature C3v out vs i out over temperature (v in = 5v) open-loop current vs temperature (ltc1983-5) temperature ( c) ?0 4.9 4.7 4.5 4.3 4.1 3.9 3.7 3.5 1983 g07 10 60 110 i in (ma) v in = 5v burst mode current vs temperature (LTC1983-3) temperature ( c) ?0 i in ( a) 25 30 35 1983 g08 20 15 10 10 60 40 45 50 110 v in = 5v open-loop input current vs v in (ltc1983-5) v in (v) 2.3 1.5 i in (ma) 2.0 2.5 3.0 3.5 4.5 2.8 3.3 3.3 4.3 1983 g09 4.8 4.0 t a = 25 c
LTC1983-3/ltc1983-5 4 sn1983 1983fs typical perfor a ce characteristics uw burst mode input current vs v in (LTC1983-3) v in (v) 3.1 26.5 input current ( a) 27.0 28.0 28.5 29.0 4.1 5.1 5.5 31.0 1983 g10 27.5 3.6 4.6 29.5 30.0 30.5 t a = 25 c temperature ( c) ?0 r out ( ) 10 12 14 150 1983 g11 8 6 0 0 50 100 4 2 18 16 v in = 5v v in = 3v i out = 10ma temperature ( c) ?0 0 v threshold (v) 0.1 0.3 0.4 0.5 1.0 0.7 0 50 1983 g12 0.2 0.8 0.9 0.6 100 150 r out vs temperature (i out = 10ma) shdn pin threshold voltage vs temperature shdn pin input current vs temperature r out vs c fly (v in = 5v) temperature ( c) ?0 2.0 2.5 3.5 100 1983 g13 1.5 1.0 0 50 150 0.5 0 3.0 i shdn c fly ( f) 0.01 1400 v in = 5v t a = 25 c 1200 1000 800 600 400 200 1983 g14 0.1 1 0 r out ( ) v out start-up into 100ma resistive load v out ripple at 100ma load v out ripple at 30ma load v out load step reponse from i out = 0 to i out = 100ma v out 1v v in 5v v out 20mv 50 m s/div 1983 g15 1 m s/div 1983 g16 v out 20mv 2.5 m s/div 1983 g17 v out 20mv 100 m s/div 1983 g18 i out 100ma
LTC1983-3/ltc1983-5 5 sn1983 1983fs uu u pi fu ctio s v in (pin 1): charge pump input voltage. may be between 2.3v and 5.5v. v in should be bypassed with a 3 4.7 m f low esr capacitor as close as possible to the pin for best performance. v out (pin 2): regulated output voltage for the ic. v out should be bypassed with a 3 4.7 m f low esr capacitor as close as possible to the pin for best performance. c + (pin 3): charge pump flying capacitor positive termi- nal. this node is switched between v in and gnd (it is connected to v cc during shutdown). c C (pin 4): charge pump flying capacitor negative termi- nal. this node is switched between gnd and v out (it is connected to gnd during shutdown). gnd (pin 5): signal and power ground for the 6-pin sot-23 package. this pin should be tied to a ground plane for best performance. shdn (pin 6): shutdown. grounding this pin shuts down the ic. tie to v in to enable. this pin should not be pulled above the v in voltage or below gnd. block diagra w control logic clock2 clock1 s1a s2a s1b s2b + v ref charge pump shdn v in c in 10 f c fly 1 f c out 10 f ltc1983-x c + c v out comp1 1 a 1983 bd
LTC1983-3/ltc1983-5 6 sn1983 1983fs operatio u the LTC1983-3/ltc1983-5 use a switched capacitor charge pump to invert a positive input voltage to a regu- lated C3v 4% (LTC1983-3) or C5 4% (ltc1983-5) output voltage. regulation is achieved by sensing the output voltage through an internal resistor divider and enabling the charge pump when the output voltage droops above the upper trip point of comp1. when the charge pump is enabled, a 2-phase, nonoverlapping clock con- trols the charge pump switches. clock 1 closes the s1 switches which enables the flying capacitor to charge up to the v in voltage. clock 2 closes the s2 switches that invert the v in voltage and connect the bottom plate of c fly to the output capacitor at v out . this sequence of charging and discharging continues at a free-running frequency of 900khz (typ) until the output voltage has been pumped down to the lower trip point of comp1 and the charge pump is disabled. when the charge pump is disabled, the ltc1983 draws only 25 m a (typ) from v in which provides high efficiency at low load conditions. in shutdown mode, all circuitry is turned off and the part draws less than 1 m a from the v in supply. v out is also disconnected from v in and c fly . the shdn pin has a threshold of approximately 0.7v. the part enters shut- down when a low is applied to the shdn pin . the shdn pin should not be floated; it must be driven with a logic high or low. open-loop operation the LTC1983-3/ltc1983-5 inverting charge pumps regu- late at C3v/C5v respectively, unless the input voltage is too low or the output current is too high. the equations for output voltage regulation are as follows: v in C5.06v > i out ? r out (ltc1983-5) v in C3.06v > i out ? r out (LTC1983-3) if this condition is not met, then the part will run in open loop mode and act as a low output impedance inverter for which the output voltage will be: v out = C[v in C(i out ? r out )] for all r out values, check the corresponding curves in the typical performance characteristics section (note: c fly = 1 m f for all r out curves). the r out value will be different for different flying caps, as shown in the follow- ing equation: r r curve fc out out osc fly =w+ ? ? ? ? (). 111 1 short-circuit/thermal protection during short-circuit conditions, the ltc1983 will draw several hundred milliamps from v in causing a rise in the junction temperature. on-chip thermal shutdown cir- cuitry disables the charge pump once the junction tem- perature exceeds ? 155 c, and reenables the charge pump once the junction temperature falls back to ? 145 c. the ltc1983 will cycle in and out of thermal shutdown indefinitely without latchup or damage until the v out short is removed. capacitor selection for best performance, it is recommended that low esr capacitors be used for both c in and c out to reduce noise and ripple. the c in and c out capacitors should be either ceramic or tantalum and should be 4.7 m f or greater. aluminum electrolytic are not recommended because of their high equivalent series resistance (esr). if the source impedance is very low, c in may not be needed. increasing the size of c out to 10 m f or greater will reduce output voltage ripple. the flying capacitor and c out should also have low equivalent series inductance (esl). the board layout is critical as well for inductance for the same reason (the suggested board layout should be used). a ceramic capacitor is recommended for the flying capaci- tor with a value in the range of 0.1 m f to 4.7 m f. note that a large value flying cap (>1 m f) will increase output ripple unless c out is also increased. for very low load applica- tions, c1 may be reduced to 0.01 m f to 0.047 m f. this will reduce output ripple at the expense of efficiency and maximum output current. (refer to block diagram)
LTC1983-3/ltc1983-5 7 sn1983 1983fs there are many aspects of the capacitors that must be taken into account. first, the temperature stability of the dielectric is a main concern. for ceramic capacitors, a three character code specifies the temperature stability (e.g. x7r, y5v, etc.). the first two characters represent the temperature range that the capacitor is specified and the third represents the absolute tolerance that the ca- pacitor is specified to over that temperature range. the ceramic capacitor used for the flying and output capaci- tors should be x5r or better . second, the voltage coef- ficient of capacitance for the capacitor must be checked and the actual value usually needs to be derated for the operating voltage (the actual value has to be larger than the value needed to take into account the loss of capaci- tance due to voltage bias across the capacitor). third, the frequency characteristics need to be taken into account because capacitance goes down as the frequency of oscillation goes up. typically, the manufacturers have capacitance vs frequency curves for their products. this curve must be referenced to be sure the capacitance will not be too small for the application. finally, the capacitor esr and esl must be low for reasons mentioned in the following section. output ripple normal ltc1983 operation produces voltage ripple on the v out pin. output voltage ripple is required for the ltc1983 to regulate. low frequency ripple exists due to the hyster- esis in the sense comparator and propagation delays in the charge pump enable/disable circuits. high frequency ripple is also present mainly due to esr of the output capacitor. typical output ripple under maximum load is 60mv p-p with a low esr 10 m f output capacitor. the magnitude of the ripple voltage depends on several factors. high input voltage to negative output voltage differentials [(v in + v out ) >1v] increase the output ripple since more charge is delivered to c out per clock cycle. a large flying capacitor (>1 m f) also increases ripple for the same reason. large output current load and/or a small output capacitor (<10 m f) results in higher ripple due to higher output voltage dv/dt. high esr capacitors (esr > 0.1 w ) on the output pin cause high frequency voltage spikes on v out with every clock cycle. there are several ways to reduce the output voltage ripple. a larger c out capacitor (22 m f or greater) will reduce both the low and high frequency ripple due to the lower c out charging and discharging dv/dt and the lower esr typi- cally found with higher value (larger case size) capacitors. a low esr ceramic output capacitor will minimize the high frequency ripple, but will not reduce the low frequency ripple unless a high capacitance value is chosen. a reason- able compromise is to use a 10 m f to 22 m f tantalum capacitor in parallel with a 1 m f to 4.7 m f ceramic capacitor on v out to reduce both the low and high frequency ripple. however, the best solution is to use 10 m f to 22 m f, x5r ceramic capacitors which are available in 1206 package sizes. an rc filter may also be used to reduce high frequency voltage spikes (see figure 1). in low load or high v in applications, smaller values for c fly may be used to reduce output ripple. a smaller flying capacitor (0.01 m f to 0.047 m f) delivers less charge per clock cycle to the output capacitor resulting in lower output ripple. however, the smaller value flying caps also reduce the maximum i out capability as well as efficiency. figure 1. output ripple reduction techniques v out v out ltc1983-x 10 f tantalum 10 f tantalum v out v out ltc1983-x 15 f tantalum 1 f ceramic 3.9 1983 f01 operatio u (refer to block diagram)
LTC1983-3/ltc1983-5 8 sn1983 1983fs inrush currents during normal operation, v in will experience current tran- sients in the several hundred milliamp range whenever the charge pump is enabled. during start-up, these inrush currents may approach 1 to 2 amps. for this reason, it is important to minimize the source resistance between the input supply and the v in pin. too much source resistance may result in regulation problems or even prevent start- up. one way that this can be avoided (especially when the source impedance cant be lowered due to system con- straints) is to use a large v in capacitor with low esr right at the v in pin. if ceramic capacitors are used, you may need to add 1 m f to 10 m f tantalum capacitor in parallel to limit input voltage transients. input voltage transients will occur if v in is applied via a switch or a plug. one example of this situation is in usb applications. ultralow quiescent current regulated supply the ltc1983 contains an internal resistor divider (refer to the block diagram) that draws only 1 m a (typ for the 3v version) from v out during normal operation. during shut- down, the resistor divider is disconnected from the output and the part draws only leakage current from the output. during no-load conditions, applying a 1hz to 100hz, 2% to 5% duty cycle signal to the shdn pin ensures that the circuit of figure 2 comes out of shutdown frequently enough to maintain regulation even under low-load condi- tions. since the part spends nearly all of its time in shutdown, the no-load quiescent current is essentially zero. however, the part will still be in operation during the time the shdn pin is high, so the current will not be zero and can be calculated using the following equations to determine the approximate maximum current: i in(max) = [(time out of shutdown) ? (burst mode operation quies- cent current) + (normal operating i in ) ? (time output is being charged before the ltc1983 enters burst mode operation)]/(period of shdn signal). this number will be highly dependent on the amount of board leakage current and how many devices are connected to v out (each will draw some leakage current) and must be calculated and verified for each different board design. the ltc1983 must be out of shutdown for a minimum duration of 200 m s to allow enough time to sense the output and keep it in regulation. a 1hz, 2% duty cycle signal will keep v out in regulation under no-load conditions. even though the term no-load is used, there will always be board leakage current and leakage current drawn by anything connected to v out . this is why it is necessary to wake the part up every once in a while to verify regulation. as the v out load current increases, the frequency with which the part is taken out of shutdown must also be increased to prevent v out from drooping below the C 2.88v (for the 3v version) during the off phase (see figure 3). a 100hz, 2% duty cycle signal on the shdn pin ensures proper regula- tion with load currents as high as 100 m a. when load current greater than 100 m a is needed, the shdn pin must be forced high as in normal operation. each time the ltc1983 comes out of shutdown, the part delivers a minimum of one clock cycle worth of charge to the output. under high v in (>4v) and/or low i out (<10 m a) conditions, this behavior may cause a net excess of charge to be delivered to the output capacitor if a high frequency signal is used on the shdn pin (e.g., 50hz to 100hz). under such conditions, v out will slowly drift positive and may even go out of regulation. to avoid this potential figure 2. ultralow quiescent current regulated supply v in gnd c + shdn v out c LTC1983-3 c fly 1 f ceramic from mpu shdn v in c in 10 f tantalum c out 10 f ceramic shdn pin waveforms: low i q mode (i out 100 a) v out load enable mode (i out = 100 a to 100ma) (1hz to 100hz, 2% to 5% duty cycle) ?v 4% 1983 f02 3.3v to 5.5v operatio u (refer to block diagram)
LTC1983-3/ltc1983-5 9 sn1983 1983fs problem in the low i q mode, it is necessary to switch the part in and out of shutdown at the minimum allowable frequency (refer to figure 3) for a given output load. general layout considerations due to the high switching frequency and high transient currents produced by the ltc1983, careful board layout is a must. a clean board layout using a ground plane and short connections to all capacitors will improve perfor- mance and ensure proper regulation under all conditions (refer to figures 4a and 4b). you will not get advertised performance with careless layout. figure 3 output current ( m a) 1 10 100 1000 maximum shdn off time (ms) 1000 1983 f03b 1 10 100 shdn on pulse width = 200 m s c out = 10 f figure 4a. recommended component placement for a single layer board figure 4b. recommended component placement for a double layer board 1 v in 2 v out 3 c + shdn 6 gnd 5 c ? 4 c out c fly v in : 2.3v to 5.5v v out 1983 f04a c in 1 v in 2 v out 3 c + shdn 6 gnd 5 c ? 4 c in c out c fly v out 1983 f04b bottom layer top layer operatio u (refer to block diagram)
LTC1983-3/ltc1983-5 10 sn1983 1983fs typical applicatio s u v in shdn c + v out gnd c ltc1983-5 v in 2.5v to 5.5v v out ? in 10 f 10 f ceramic 1 f ceramic off on 1983 ta04 v in shdn c + v out gnd c ltc1983-5 v in 2.5v v out ?.5v 1 f ceramic 4.7 f ceramic 0.47 f ceramic off on 1983 ta03 2.5v to C2.5v dc/dc converter 100ma inverting dc/dc converter
LTC1983-3/ltc1983-5 11 sn1983 1983fs package descriptio u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s6 package 6-lead plastic sot-23 (reference ltc dwg # 05-08-1636) 1.50 ?1.75 (note 4) 2.80 bsc 0.30 ?0.45 typ 6 plcs (note 3) datum ? 0.09 ?0.20 (note 3) s6 tsot-23 0801 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ?0.90 1.00 max 0.01 ?0.10 0.20 bsc 0.30 ?0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.254 0.754 0.95 bsc 0.854 0.127 recommended solder pad layout 1.9 bsc
LTC1983-3/ltc1983-5 12 sn1983 1983fs linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2002 lt/tp 0302 2k ? printed in usa related parts part number description comments ltc1261 switched-capacitor regulated voltage inverter selectable fixed output voltages ltc1261l switched-capacitor regulated voltage inverter adjustable and fixed output voltages, up to 20ma i out , msop ltc1429 clock-synchronized switched-capacitor voltage inverter synchronizable up to 2mhz system clock ltc1514/ltc1515 step-up/step-down switched-capacitor dc/dc converters v in 2v to 10v, adjustable or fixed v out , i out to 50ma ltc1516 micropower regulated 5v charge pump dc/dc converter i out = 20ma (v in 3 2v), i out = 50ma (v in 3 3v) ltc1522 micropower regulated 5v charge pump dc/dc converter i out = 10ma (v in 3 2.7v), i out = 20ma (v in 3 3v) ltc1550l/ltc1551l low noise, switched-capacitor regulated voltage inverters 900khz charge pump, 1mv p-p ripple lt1611 1.4mhz inverting mode switching regulator C5v at 150ma from a 5v input, 5-lead thinsot lt1617/lt1617-1 micropower, switched-capacitor voltage inverter v in 1.2v/1v to 15v; 350ma/100ma current limit ltc1682/-3.3/-5 doubler charge pumps with low noise ldo ms8 and so-8 packages, i out = 80ma, output noise = 60 m v rms ltc1751/-3.3/-5 doubler charge pumps v out =5v at 100ma; v out =3.3v at 80ma; adj; msop packages ltc1754/-3.3/-5 doubler charge pumps with shutdown thinsot package; i q = 13 m a; i out = 50ma ltc1928-5 doubler charge pump with low noise ldo thinsot output noise = 60 m v rms ; v out = 5v; v in = 2.7v to 4v ltc3200 constant frequency doubler charge pump low noise, 5v output or adjustable combined unregulated doubler and regulated inverter u typical applicatio c + c LTC1983-3/ ltc1983-5 c fly 1 f ceramic c boost 1 f off on c out2 10 f ceramic c out1 10 f ceramic c in 10 f ceramic 1983 ta05 v in v in v out v out shdn gnd d1 d2 v boost v boost = 2v in ?(v d )

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